Remove support for IBM's XL C compiler

We really only support building Unit with GCC and Clang.

Cc: Dan Callahan <d.callahan@f5.com>
Reviewed-by: Alejandro Colomar <alx@kernel.org>
Signed-off-by: Andrew Clayton <a.clayton@nginx.com>

3 files changed, 1 insertions, 176 deletions

diff --git a/auto/atomic b/auto/atomic
index f99adf7e..7acd4667 100644
--- a/auto/atomic
+++ b/auto/atomic
@@ -65,55 +65,6 @@ if [ $nxt_found = no ]; then
 fi
 
 
-# AIX xlC builtin atomic operations.
-
-if [ $nxt_found = no ]; then
-
-    if [ $NXT_64BIT = 1 ]; then
-        nxt_feature_test="int main(void) {
-                              long  n = 0;
-                              long  o = 0;
-
-                              if (!__compare_and_swaplp(&n, &o, 3))
-                                  return 1;
-                              if (__fetch_and_addlp(&n, 1) != 3)
-                                  return 1;
-                              if (__fetch_and_swaplp(&n, 5) != 4)
-                                  return 1;
-                              if (n != 5)
-                                  return 1;
-                              __isync();
-                              __lwsync();
-                              return 0;
-                          }"
-    else
-        nxt_feature_test="int main(void) {
-                              int  n = 0;
-                              int  o = 0;
-
-                              if (!__compare_and_swap(&n, &o, 3))
-                                  return 1;
-                              if (__fetch_and_add(&n, 1) != 3)
-                                  return 1;
-                              if (__fetch_and_swap(&n, 5) != 4)
-                                  return 1;
-                              if (n != 5)
-                                  return 1;
-                              __isync();
-                              __lwsync();
-                              return 0;
-                          }"
-    fi
-
-    nxt_feature="xlC builtin atomic operations"
-    nxt_feature_name=NXT_HAVE_XLC_ATOMIC
-    nxt_feature_run=yes
-    nxt_feature_incs=
-    nxt_feature_libs=
-    . auto/feature
-fi
-
-
 if [ $nxt_found = no ]; then
     $echo
     $echo $0: error: no atomic operations found.
diff --git a/auto/cc/test b/auto/cc/test
index b1745505..499a2fb1 100644
--- a/auto/cc/test
+++ b/auto/cc/test
@@ -54,19 +54,9 @@ then
     $echo " + $NXT_CC_VERSION"
 
 else
-if `/bin/sh -c "($CC -qversion)" 2>&1 \
-                | grep "^IBM XL" >> $NXT_AUTOCONF_ERR 2>&1`
-then
-    NXT_CC_NAME=xlC
-    $echo " + using AIX xlC compiler"
-    NXT_CC_VERSION=`/bin/sh -c "($CC -qversion)" 2>&1 | grep "IBM XL" 2>&1`
-    $echo " + $NXT_CC_VERSION"
-
-else
     NXT_CC_NAME=cc
     NXT_CC_VERSION=cc
 
-fi # xlC
 fi # SunC
 fi # Apple LLVM clang
 fi # clang
@@ -163,20 +153,6 @@ case $NXT_CC_NAME in
         NXT_CFLAGS="$NXT_CFLAGS -g"
     ;;
 
-    xlC)
-        nxt_have=NXT_XLC . auto/have
-
-        #NXT_CFLAGS="$NXT_CFLAGS -qalloca"
-        # alloca support.
-        NXT_CFLAGS="$NXT_CFLAGS -qlanglvl=extc99"
-        # __thread support.
-        NXT_CFLAGS="$NXT_CFLAGS -qtls"
-        # Suppress warning
-        #    1506-159 (E) Bit field type specified for XXX is not valid.
-        #    Type unsigned assumed.
-        NXT_CFLAGS="$NXT_CFLAGS -qsuppress=1506-159"
-    ;;
-
     *)
     ;;
 
diff --git a/src/nxt_atomic.h b/src/nxt_atomic.h
index dae999a9..585d0be2 100644
--- a/src/nxt_atomic.h
+++ b/src/nxt_atomic.h
@@ -161,109 +161,7 @@ typedef volatile nxt_atomic_uint_t  nxt_atomic_t;
  */
 
 
-#elif (NXT_HAVE_XLC_ATOMIC) /* XL C/C++ V8.0 for AIX */
-
-#if (NXT_64BIT)
-
-typedef long                        nxt_atomic_int_t;
-typedef unsigned long               nxt_atomic_uint_t;
-typedef volatile nxt_atomic_int_t   nxt_atomic_t;
-
-
-nxt_inline nxt_bool_t
-nxt_atomic_cmp_set(nxt_atomic_t *lock, nxt_atomic_int_t cmp,
-    nxt_atomic_int_t set)
-{
-    nxt_atomic_int_t  old;
-
-    old = cmp;
-
-    return __compare_and_swaplp(lock, &old, set);
-}
-
-
-#define nxt_atomic_xchg(lock, set)                                            \
-    __fetch_and_swaplp(lock, set)
-
-
-#define nxt_atomic_fetch_add(value, add)                                      \
-    __fetch_and_addlp(value, add)
-
-
-#else /* NXT_32BIT */
-
-typedef int                         nxt_atomic_int_t;
-typedef unsigned int                nxt_atomic_uint_t;
-typedef volatile nxt_atomic_int_t   nxt_atomic_t;
-
-
-nxt_inline nxt_bool_t
-nxt_atomic_cmp_set(nxt_atomic_t *lock, nxt_atomic_int_t cmp,
-    nxt_atomic_int_t set)
-{
-    nxt_atomic_int_t  old;
-
-    old = cmp;
-
-    return __compare_and_swap(lock, &old, set);
-}
-
-
-#define nxt_atomic_xchg(lock, set)                                            \
-    __fetch_and_swap(lock, set)
-
-
-#define nxt_atomic_fetch_add(value, add)                                      \
-    __fetch_and_add(value, add)
-
-
-#endif /* NXT_32BIT*/
-
-
-/*
- * __lwsync() is a "lwsync" instruction that sets #LoadLoad, #LoadStore,
- * and #StoreStore barrier.
- *
- * __compare_and_swap() is a pair of "ldarx" and "stdcx" instructions.
- * A "lwsync" does not set #StoreLoad barrier so it can not be used after
- * this pair since a next load inside critical section can be performed
- * after the "ldarx" instruction but before the "stdcx" instruction.
- * However, this next load instruction will load correct data because
- * otherwise the "ldarx/stdcx" pair will fail and this data will be
- * discarded.  Nevertheless, the "isync" instruction is used for sure.
- *
- * A full barrier can be set with __sync(), a "sync" instruction, but there
- * is also a faster __isync(), an "isync" instruction.  This instruction is
- * not a memory barrier but an instruction barrier.  An "isync" instruction
- * causes the processor to complete execution of all previous instructions
- * and then to discard instructions (which may have begun execution) following
- * the "isync".  After the "isync" is executed, the following instructions
- * then begin execution.  The "isync" is used to ensure that the loads
- * following entry into a critical section are not performed (because of
- * aggressive out-of-order or speculative execution in the processor) until
- * the lock is granted.
- */
-
-nxt_inline nxt_bool_t
-nxt_atomic_try_lock(nxt_atomic_t *lock)
-{
-    if (nxt_atomic_cmp_set(lock, 0, 1)) {
-        __isync();
-        return 1;
-    }
-
-    return 0;
-}
-
-
-#define nxt_atomic_release(lock)                                              \
-    do { __lwsync(); *lock = 0; } while (0)
-
-
-#define nxt_cpu_pause()
-
-
-#endif /* NXT_HAVE_XLC_ATOMIC */
+#endif /* NXT_HAVE_GCC_ATOMIC */
 
 
 #endif /* _NXT_ATOMIC_H_INCLUDED_ */